The present invention generally relates to a display apparatus of a mobile appliance such as cellular telephones. More specifically, the present invention is directed to a liquid crystal display device capable of realizing a high picture quality and operable in low power consumption.
As a driving method for making a display on a so-called “partial display area” of a display panel and also for making a partial display on other display areas of this display panel, in which the background is displayed, the below-mentioned driving method has been disclosed in, for example, JP-A-2001-356746. That is, while a display device is equipped with a plurality of pixels formed in a matrix of “n” rows and “m” columns, the display device performs a so-called “partial display” operation in a partial screen area which is constituted by arbitrarily selected pixels made of “s” rows and “m” columns, and also displays the background on a background screen area made of the above-described “n” rows and “m” columns. In the driving method for the above-described display device, when a partial display mode is selected, the above-explained partial display data is written in the respective pixels of the partial screen area constituted by the above-described “s” rows and “m” columns, and also, background display data are written in pixels made of “k” rows and “m” columns within the background display area during 1 frame period. It should be understood that all of symbols “n”, “m”, “s”, and “k” represent integers larger than, or equal to 1, and further, mutual relationships are given by s<n, and k<n.
Also, JP-A-2002-182619 discloses the below-mentioned method of driving the display device. That is, in this driving method, while a break period is provided in any periods other than a scanning period, since an effective voltage applied to a liquid crystal layer is made equal to an effective voltage within this break period, the flickering may be suppressed and power consumption may be lowered.
The above-described patent publication of JP-A-2001-356746 does not describe a driving method capable of suppressing deteriorations in picture qualities, and more specifically, capable of suppressing the flickering. Also, the above-explained patent publication of JP-A-2002-182619 does not describe a driving method for performing a partial display operation.
Referring now to FIG. 10A through FIG. 12, problems to be solved by the present invention will be described.
In a liquid crystal display device of a cellular telephone operated in a standby mode, only limited contents of such information as an antenna sensitivity and a battery level may be sometimes displayed on a portion of a liquid crystal display panel of the liquid crystal display apparatus (namely, partial display operation).
FIG. 10A is a schematic block diagram of a liquid crystal display device 1 which performs such a display operation shown in FIG. 10B. FIG. 10B to FIG. 10E represent display examples as to display conditions in a liquid crystal display panel having pixels which are constructed of “N” rows and “M” columns in a matrix form. It should be noted that symbols “N” and “M” indicate integers larger than, or equal to 1.
The liquid crystal display device 1 contains a liquid crystal panel 2, a source driver 3, a gate driver 4, and a power supply circuit 5. These circuits may be provided in separate LSIs, a portion of these circuits may be alternatively provided in partially commonly used LSIs, or all of these circuits may be alternatively provided in a commonly used LSI. Also, either a portion or all of these circuits may be alternatively built in a liquid crystal panel. In this specification, the below-mentioned explanations will be made in such a case that these circuits are provided in the separate LSIs.
In the liquid crystal panel 2, an area where a partial display operation is carried out will be referred to as a “partial display area”, whereas an area other than the partial display area will be referred to as a “background display area.” Such an operation that a partial display is performed will be referred as a “partial display mode.”
Under a display condition of FIG. 10B, while a partial display is performed by employing a gate line of a first row up to a gate line of an “(i0)-th” row, a certain potential corresponding to the background has been held, or applied to such pixels which are connected from a gate line of an (i0+1)-th row up to a gate line of an N-th row; and thus, the background has been displayed. When the background display area is scanned, voltages which are applied to the liquid crystal of the background display area are equal to each other at the most pixels of the background display area, and the background display area displays the substantially same color and the substantially same luminance.
In the case of FIG. 10C, in a foldable type cellular telephone, two liquid crystal panels are provided which are constituted by a main panel 2′ and a sub-panel 2″. Various sorts of setting operations as to the cellular telephone are performed on the main panel 2′. Information is displayed on the sub-panel 2″ even under folded condition. A data line is commonly used for both the main panel 2′ and the sub-panel 2″.
The condition of FIG. 10C corresponds to such a case that the cellular telephone has been folded, and the entire screen of the main panel 2′ corresponds to the background display area. The partial display area corresponds to such areas defined from an (i1)-th row to an (i2)-th row of the sub-panel 2″, and the background display area corresponds to such an area defined by the remaining rows of the sub-panel 2″.
In the case of FIG. 10D, an (i3)-th row to an (i4)-th row of the main panel 2 correspond to the partial display area, whereas the remaining rows of the main panel 2 correspond to the background display area.
In the case of FIG. 10E, two partial display areas are present which are defined from a first row up to an (i5)-th row of the main panel 2, and from an (i6)-th row up to an (i7)-th row of the main panel 2. A background display area is defined by the remaining rows of the main panel 2. It should be understood that in FIG. 10A to FIG. 10E, symbols “i0”, “i1”, --- , “i6”, and “i7” indicate integers larger than, or equal to 2.
In the below-mentioned descriptions, the display mode of the liquid crystal panel 2 is assumed to as a “normally open.” First of all, operations of the normal case in which the entire screen of the liquid crystal panel 2 is displayed are summarized. This normal case will be referred to as a “normal display mode” hereinafter, and a time period during which a gate line is scanned. Also, in such a case that a cellular telephone owns two display screens and a data line is commonly used in both a main panel 2′ and a sub-panel 2″, when information is displayed on the main panel 2′, the display mode of the liquid crystal panel 2 corresponds to the normal display mode. In this case, such a time period during which the gate line of the main panel 2′ is scanned will be referred to as a frame period, whereas a time period during which one row is scanned in the gate lines of the main panel 2′ will be referred to as a period “Thn” for scanning one row.
FIG. 11A indicates an equivalent circuit diagram as to 1 pixel defined by an “n” row, and an “m” column. FIG. 11B represents a driving method diagram as to a data line potential “Vdm”, a common electrode potential “Vcom”, and gate line potentials “Vg1” to “VgN”; and shows an absolute value “Valc” (will be simply referred to as “voltage Valc” hereinafter) between a pixel electrode potential “Vpix” and the common electrode potential “Vcom” of the pixel defined by the “n” row and the “m” column; and also indicates an optical response of the pixel defined by the “n” row/“m” column.
The source driver 3 produces a grayscale voltage while the ground potential 0 V is used as a reference potential. Both the data line potential Vdm and the common electrode potential Vcom have been drawn while this potential is used as a reference potential. In the below-mentioned explanations, references (0 V) of the respective potentials are defined as the ground potential. It should also be understood that in the respective drawings except for FIG. 5, the gate line potentials Vg1 to VgN are illustrated as simplified pulses, while an attention has been paid only to timing, but are not illustrated while the ground potential is employed as the reference potential.
The equivalent circuit shown in FIG. 11A is explained. In this equivalent circuit, an active element functioning as a switch is present at an intersection portion between a data line (signal line) 101 and a gate line (scanning line) 102, and this active element is made of a thin-film transistor (will be referred to as “TFT” hereinafter) in this example.
While the gate line 102 controls turning ON/OFF of the TFT, when the gate line potential “Vgn” of the n-th row becomes “high” (high potential becomes approximately 10 V to 15 V), the TFT is under ON state, and the circuit between the data line 101 and the pixel electrode becomes conductive, so that the data line potential Vdm of the m-th column is applied to the pixel electrode.
When the gate line potential Vgn of the n-th row becomes “low” (low potential becomes approximately 0 V to −15 V), the TFT is under OFF state. A line between the data line 101 and the pixel electrode is brought into a high resistance condition, and thus, an electron charge of the pixel is held. The TFT under OFF state may be expressed as a resistor “Roff” which is connected to the data line 101 and the pixel electrode.
While liquid crystal is represented by a parallel circuit constructed of a liquid crystal capacitor “C1c” and a liquid crystal resistor “R1c”, a voltage between the pixel electrode and the common electrode 100 is applied to the liquid crystal. A storage capacitor “Cstg” for holding an electron charge is arranged between a storage line 103 and the pixel electrode. A parasitic capacitor “Csd1” is present between the pixel electrode and the data line 101 which is connected to the TFT of the pixel, and another parasitic capacitor “Csd2” is present between the pixel electrode and a data line which is located opposite to the data line 101 connected to the TFT of the pixel while sandwiching the pixel electrode of the pixel. Also, another parasitic capacitor “Cgs” is present between the pixel electrode and the gate line 102. Since the parasitic capacitors are present, when the potential on the data line 101 and the potential on the gate line 102 are varied, the pixel electrode potential is varied due to capacitive coupling, so that an optical response change may be caused. Also, even when the TFT is under OFF state, a leak current will flow because both the resistor “Roff” and the liquid crystal register “R1c” are present, so that the pixel electrode potential is varied.
Next, a description is made of the driving method diagram for two continued frames shown in FIG. 11B. In a frame period “Tf”, the common electrode potential Vcom becomes either a potential “VcomH” or another potential “VcomL”. It is so assumed that such a frame when the common electrode potential Vcom becomes the potential VcomL is referred to as a positive frame, and a frame when the common electrode potential Vcom becomes the potential VcomH is referred to as a negative frame. The common electrode potential Vcom is inverted every frame. The data line potential Vdm becomes such a potential in correspondence with a potential of image data. In this drawing, the data line potential Vdm represents such a case that a black color is displayed on the entire screen of the liquid crystal panel. Symbols “Vg1” to “VgN” show gate line potentials from the first row to the N-th row.
Now, a description is made of temporal changes as to the voltage Valc. When the gate line potential Vgn of the n-th row becomes “high”, a predetermined voltage is applied. Thereafter, when the gate line potential Vgn becomes “low”, in such a case that the gate line potential Vgn is transferred from “high” to “low”, the pixel electrode potential is decreased only by “ΔVft” due to the capacitive coupling via the parasitic capacitor Cgs. It should also be noted that symbol “ΔVft” implies a magnitude of a potential drop, and will be referred to as a “feed-through voltage” hereinafter.
In the case of the negative frame, the voltage Valc is increased only by ΔVft, whereas in the case of the positive frame, the voltage Valc is decreased only by ΔVft. More specifically, this phenomenon will be called as a “feed-through” phenomenon. Since this field-through phenomenon is present, while both an amplitude center potential Vcomc of the common electrode potential “Vcom” and a center potential “Vcen” of the data line potential Vdm are made different from each other, the amplitude center potential Vcomc of the common electrode potential Vcom is made lower than the center potential Vcen of the data line potential Vdm by approximately ΔVft.
Since the above-explained potential setting operation is carried out, the voltages Valc just after the gate line potential Vgm is changed form “high” to “low” may become equal to each other in both the positive frame and the negative frame. After the voltage Valc has been written, this voltage may maintain an essentially desirable voltage when the frames are switched. Since both the common electrode potential Vcom and the data line potential Vdm are varied when the frames are switched, a voltage variation of the voltage Valc also occurs. Display luminance is also varied in synchronism with the variation of the voltage Valc. In the temporal changes in the voltage Valc, an adverse influence caused by the leak current is neglected. In such a case that a leak current is large, a voltage drop caused by this large leak current may occur. In particular, when a time period for holding the voltage Valc is sufficiently longer than 1/60 seconds, the adverse influence caused by the leak current cannot be neglected. Also, the optical response change as indicated in FIG. 11B may be sometimes sensed as a flicker phenomenon. If a frame frequency is lower than, or equal to 60 Hz, then a flicker phenomenon may be easily sensed. As a result, normally, a frame frequency is selected to be higher than, or equal to 60 Hz.
Next, with reference to FIG. 12, a description is made of summarized operations in the case that a partial display operation is carried out by way of the conventional driving method in the pixels defined from an (n−np)-th row up to an (n+np)-th row, which contain the pixel of the n-th row. FIG. 12 represents a timing chart of a driving method for driving two continued frames; a voltage “Valc” of a pixel defined by an n-th row and an m-th column; and an optical response of the pixel. This timing chart of the driving method corresponds to such a case that a background display area is displayed in white and a partial display area is displayed in black.
Generally speaking, in such a case that a display mode corresponds to a normally open mode, a display operation of a background display area is set to a white display operation where a magnitude of a voltage to be applied to liquid crystal (will be referred to as “liquid crystal voltage”) becomes minimum. In such a case that a display mode corresponds to a normally close mode, a display operation of a background display area is set to a black display operation. The reason is given as follows: That is, when the liquid crystal voltage is low, even if this liquid crystal voltage is varied, a deterioration of picture qualities can hardly occur. As a consequence, the background display area is not scanned every frame, but is scanned every several frames, so that a total number of scanning operations as to the background display area may be reduced so as to achieve low power consumption.
The common electrode potential Vcom behaves the same operation as that of the normal display mode. The data line potential Vdm becomes such a potential for displaying white from a first row up to an (n−np−1)-th row; becomes such a potential for displaying black from an (n−np)-th row up to an (n+np)-th row; and again becomes such a potential for displaying white from an (n+np+1)-th row up to an N-th row.
The period during which the pixels defined from the (n−np)-th row up to the (n+np)-th row corresponding to the partial display area are scanned will be referred to as a “partially scanning period Ts.” The definitions as to both the positive frame and the negative frame during the partial display mode are changed from those during the normal display mode as follows:
In the case that the black is displayed in the partially scanning period Ts, such a frame is assumed as the positive frame, in which the common electrode potential Vcom becomes lower than the data line potential Vdm. Also, in the case that the black is displayed in the partially scanning period Ts, such a frame is assumed as the positive frame, in which the common electrode potential Vcom becomes higher than the data line potential Vdm.
If both the data line potential Vdm and the common electrode potential Vcom are varied due to the presence of the parasitic capacitor, then the voltage Valc is varied. In the case of the partial display mode by the conventional driving method, the variations of the voltage Valc may occur at least 4 times at (1) to (4) of timing shown in FIG. 12 within 1 frame period.
Similarly, changes in the optical response may occur in response to the variations of this voltage Valc, and thus, the optical response waveform may be distorted. In such a case that the optical response waveform is distorted to become a complex waveform, it is practically difficult to form the optical response waveform as a symmetrical waveform in both the positive frame and the negative frame, and thus, the period of the optical response waveform becomes two frames. As a consequence, the flickering is produced, the frequency of which is equal to a half of the frame frequency.
In particular, since a partial display operation is mainly carried out during a standby mode of a cellular telephone, the partial display operation is required to be performed in low power consumption. To achieve such a low power consumption, there are some cases that liquid crystal display devices are driven while frame frequencies thereof are decreased lower than 60 Hz. Therefore, in the above-described conventional driving method, the flickering having frequencies lower than 30 Hz may be produced. Since the flickering having such lower frequencies may be easily sensed, image qualities of liquid crystal display devices may be considerably deteriorated.